1. Field of the Invention
This invention relates in general to threshold gates w/hysteresis, and more particularly to threshold gates w/hysteresis and with embedded registration.
2. Description of Related Art
Previous logic systems, such as Boolean logic systems, have employed clocking signals to regulate the digital processing of binary logic signals. Typically, a digital logic circuit will respond to multiple inputs to generate an output. As input logic signals propagate through the sequential circuit, the sequential circuit output is unreliable for a period of time corresponding to worst case propagation delays through the individual logic gates. Typically, the output signal is sampled at a time when the output is stable, often by latching the output into a register. The sampling time is set according to an independent clock signal, i.e., one that is not derived from the states of the logic gates themselves.
Threshold logic gates are one type of sequential logic circuit which respond to multiple inputs to generate an output. Generally, threshold logic gates are employed in systems where it is necessary to generate a data value or not to generate a data value dependent on whether there are at least a predetermined number of digital input signals satisfy a given threshold criteria. Threshold logic gates can be used to provide data registration.
Traditional threshold logic gates have sometimes included a registration stage having a reset capability that allows data initiation and acknowledgment processing for determining when the data should be forwarded. However, the registration stages add another stage of data processing which increases the number of active elements in the circuit as well as decrease the processing throughput.
In addition, traditional synchronous circuits have become the dominant class of logic. However, a substantial amount of design analysis is necessary to avoid a variety of timing-related problems, such as race conditions. Furthermore, the fraction of power and real estate that must be devoted to clocking has become substantial, and in certain instances has become a limiting factor to the total amount of circuitry that can be integrated onto a single chip.
It can be seen then that there is a need for a dynamic threshold gate that reduces the number of active elements required to perform the data evaluation and registration.
It can also be seen that there is a need for a dynamic threshold gate that increases the system processing throughput by pipelining the registration at the gate-level.